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arm64: zynqmp: Disable coresight by default

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When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.

Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7e308b8efe977c4912079b4d1b1ab3d24908559e.1756799774.git.michal.simek@amd.com
This commit is contained in:
Quanyang Wang 2025-09-02 09:56:18 +02:00 committed by Michal Simek
parent 4f96c5db61
commit 0e3f9140ad
1 changed files with 4 additions and 0 deletions
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4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
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@ -550,6 +550,7 @@ cpu0_debug: debug@fec10000 {
reg = <0x0 0xfec10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
status = "disabled";
};
cpu1_debug: debug@fed10000 {
@ -557,6 +558,7 @@ cpu1_debug: debug@fed10000 {
reg = <0x0 0xfed10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu1>;
status = "disabled";
};
cpu2_debug: debug@fee10000 {
@ -564,6 +566,7 @@ cpu2_debug: debug@fee10000 {
reg = <0x0 0xfee10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu2>;
status = "disabled";
};
cpu3_debug: debug@fef10000 {
@ -571,6 +574,7 @@ cpu3_debug: debug@fef10000 {
reg = <0x0 0xfef10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu3>;
status = "disabled";
};
/* GDMA */