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arm64: zynqmp: Add support for kd240 board
The kit is using k24 SOM by default and it is used for motor control and DSP applications. K24 SOM is also possible to used with kv260 and kr260 CC which are also wired in Makefile. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/05ff505c6b6517e3aba983a21454c568c5e86389.1752837842.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
parent
7030418d4e
commit
4f96c5db61
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@ -39,4 +39,19 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb
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zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb
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zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb
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zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb
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zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb
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zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
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zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb
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zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb
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390
arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso
Normal file
390
arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso
Normal file
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@ -0,0 +1,390 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for KD240 revA Carrier Card
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*
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* Copyright (C) 2021 - 2022, Xilinx, Inc.
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* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/dts-v1/;
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/plugin/;
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&{/} {
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compatible = "xlnx,zynqmp-sk-kd240-rev1",
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"xlnx,zynqmp-sk-kd240-revB",
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"xlnx,zynqmp-sk-kd240-revA",
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"xlnx,zynqmp-sk-kd240", "xlnx,zynqmp";
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model = "ZynqMP KD240 revA/B/1";
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aliases {
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ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */
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};
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ina260-u3 {
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compatible = "iio-hwmon";
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io-channels = <&u3 0>, <&u3 1>, <&u3 2>;
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};
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clk_26: clock2 { /* u17 - USB */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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clk_25_0: clock4 { /* u92/u91 - GEM2 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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clk_25_1: clock5 { /* u92/u91 - GEM3 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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&can0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0_default>;
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};
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&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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u3: ina260@40 { /* u3 */
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compatible = "ti,ina260";
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#io-channel-cells = <1>;
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label = "ina260-u14";
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reg = <0x40>;
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};
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slg7xl45106: gpio@11 { /* u13 - reset logic */
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compatible = "dlg,slg7xl45106";
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reg = <0x11>;
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label = "resetchip";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "USB0_PHY_RESET_B", "",
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"SD_RESET_B", "USB0_HUB_RESET_B",
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"", "PS_GEM0_RESET_B",
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"", "";
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};
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hub: usb-hub@2d { /* u36 */
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compatible = "microchip,usb5744";
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reg = <0x2d>;
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};
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};
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/* USB 3.0 */
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&psgtr {
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status = "okay";
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/* usb */
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clocks = <&clk_26>;
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clock-names = "ref2";
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};
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&usb0 { /* mio52 - mio63 */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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phy-names = "usb3-phy";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
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reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
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assigned-clock-rates = <250000000>, <20000000>;
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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#address-cells = <1>;
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#size-cells = <0>;
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/* 2.0 hub on port 1 */
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hub_2_0: hub@1 {
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compatible = "usb424,2744";
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reg = <1>;
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peer-hub = <&hub_3_0>;
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i2c-bus = <&hub>;
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reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
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};
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/* 3.0 hub on port 2 */
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hub_3_0: hub@2 {
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compatible = "usb424,5744";
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reg = <2>;
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peer-hub = <&hub_2_0>;
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i2c-bus = <&hub>;
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reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
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};
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};
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&gem1 { /* mdio mio50/51 */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem1_default>;
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assigned-clock-rates = <250000000>;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@8 { /* Adin u31 */
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#phy-cells = <1>;
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compatible = "ethernet-phy-id0283.bc30";
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reg = <8>;
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adi,rx-internal-delay-ps = <2000>;
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adi,tx-internal-delay-ps = <2000>;
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adi,fifo-depth-bits = <8>;
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reset-assert-us = <10>;
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reset-deassert-us = <5000>;
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reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>;
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};
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};
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};
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/* 2 more ethernet phys u32@2 and u34@3 */
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&pinctrl0 { /* required by spec */
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status = "okay";
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pinctrl_can0_default: can0-default {
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mux {
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function = "can0";
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groups = "can0_16_grp";
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};
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conf {
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groups = "can0_16_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO66";
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bias-pull-up;
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};
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conf-tx {
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pins = "MIO67";
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bias-pull-up;
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drive-strength = <4>;
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};
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};
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pinctrl_uart0_default: uart0-default {
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conf {
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groups = "uart0_17_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO70";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO71";
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bias-disable;
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};
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mux {
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groups = "uart0_17_grp";
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function = "uart0";
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};
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};
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pinctrl_uart1_default: uart1-default {
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conf {
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groups = "uart1_9_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO37";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO36";
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bias-disable;
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output-enable;
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};
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mux {
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groups = "uart1_9_grp";
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function = "uart1";
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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conf {
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groups = "i2c1_6_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "i2c1_6_grp";
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function = "i2c1";
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio-grp {
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conf {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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function = "gpio0";
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};
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};
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pinctrl_gem1_default: gem1-default {
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conf {
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groups = "ethernet1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO45", "MIO46", "MIO47", "MIO48";
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bias-disable;
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low-power-disable;
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};
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conf-bootstrap {
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pins = "MIO44", "MIO49";
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bias-disable;
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output-enable;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO38", "MIO39", "MIO40",
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"MIO41", "MIO42", "MIO43";
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bias-disable;
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output-enable;
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low-power-enable;
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};
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conf-mdio {
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groups = "mdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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output-enable;
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};
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mux-mdio {
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function = "mdio1";
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groups = "mdio1_0_grp";
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};
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mux {
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function = "ethernet1";
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groups = "ethernet1_0_grp";
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};
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};
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pinctrl_usb0_default: usb0-default {
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conf {
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groups = "usb0_0_grp";
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO52", "MIO53", "MIO55";
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bias-high-impedance;
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drive-strength = <12>;
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slew-rate = <SLEW_RATE_FAST>;
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};
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conf-tx {
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
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"MIO60", "MIO61", "MIO62", "MIO63";
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bias-disable;
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output-enable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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};
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pinctrl_usb1_default: usb1-default {
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conf {
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groups = "usb1_0_grp";
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO64", "MIO65", "MIO67";
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bias-high-impedance;
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drive-strength = <12>;
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slew-rate = <SLEW_RATE_FAST>;
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};
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conf-tx {
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pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
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"MIO72", "MIO73", "MIO74", "MIO75";
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bias-disable;
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output-enable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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mux {
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groups = "usb1_0_grp";
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function = "usb1";
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};
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};
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};
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&uart0 {
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status = "okay";
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rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>;
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linux,rs485-enabled-at-boot-time;
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rs485-rts-delay = <10 10>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_default>;
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assigned-clock-rates = <100000000>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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&zynqmp_dpsub {
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status = "disabled";
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};
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23
arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts
Normal file
23
arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts
Normal file
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP SM-K24 RevA
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*
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* (C) Copyright 2020 - 2021, Xilinx, Inc.
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* (C) Copyright 2022, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include "zynqmp-sm-k26-revA.dts"
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/ {
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model = "ZynqMP SM-K24 RevA/B/1";
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compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB",
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"xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
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"xlnx,zynqmp";
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memory@0 {
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device_type = "memory"; /* 2GB */
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reg = <0 0 0 0x80000000>;
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};
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};
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21
arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts
Normal file
21
arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts
Normal file
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@ -0,0 +1,21 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
|
||||
* dts file for Xilinx ZynqMP SMK-K24 RevA
|
||||
*
|
||||
* (C) Copyright 2020 - 2021, Xilinx, Inc.
|
||||
* (C) Copyright 2022, Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@amd.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-sm-k24-revA.dts"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP SMK-K24 RevA";
|
||||
compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24",
|
||||
"xlnx,zynqmp";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user