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RISC-V SpacemiT DT changes for 6.14

Browse Source 
- rebase to 6.13-rc2
 - basic device tree support
 - pinctrl dt node info
 - update MAINTAINERS info
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Merge tag 'spacemit-dt-for-6.14-1' of https://github.com/spacemit-com/linux into soc/newsoc

RISC-V SpacemiT DT changes for 6.14

This adds support for the SpacemiT K1 SoC and the Banana Pi F3
board using it:

- basic device tree support
- pinctrl dt node info
- update MAINTAINERS info

* tag 'spacemit-dt-for-6.14-1' of https://github.com/spacemit-com/linux:
  riscv: dts: spacemit: move aliases to board dts
  riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
  riscv: defconfig: enable SpacemiT SoC
  riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree
  riscv: dts: add initial SpacemiT K1 SoC device tree
  riscv: add SpacemiT SoC family Kconfig support
  dt-bindings: serial: 8250: Add SpacemiT K1 uart compatible
  dt-bindings: interrupt-controller: Add SpacemiT K1 PLIC
  dt-bindings: timer: Add SpacemiT K1 CLINT
  dt-bindings: riscv: add SpacemiT K1 bindings
  dt-bindings: riscv: Add SpacemiT X60 compatibles
  MAINTAINERS: setup support for SpacemiT SoC tree

Link: https://wiki.banana-pi.org/Banana_Pi_BPI-F3
Link: https://www.spacemit.com/en/key-stone-k1/
Link: https://lore.kernel.org/r/20250117004911-GYA25021@gentoo
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-01-23 17:33:19 +01:00
commit 0bcf3ac146
13 changed files with 550 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@ -59,6 +59,7 @@ properties:
- enum:
- canaan,k210-plic
- sifive,fu540-c000-plic
- spacemit,k1-plic
- starfive,jh7100-plic
- starfive,jh7110-plic
- const: sifive,plic-1.0.0

1
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@ -46,6 +46,7 @@ properties:
- sifive,u7
- sifive,u74
- sifive,u74-mc
- spacemit,x60
- thead,c906
- thead,c908
- thead,c910

28
Documentation/devicetree/bindings/riscv/spacemit.yaml Normal file
View File

@ -0,0 +1,28 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/spacemit.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT SoC-based boards
maintainers:
- Yangyu Chen <cyy@cyyself.name>
- Yixun Lan <dlan@gentoo.org>
description:
SpacemiT SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- bananapi,bpi-f3
- const: spacemit,k1
additionalProperties: true
...

4
Documentation/devicetree/bindings/serial/8250.yaml
View File

@ -111,7 +111,9 @@ properties:
- mediatek,mt7623-btif
- const: mediatek,mtk-btif
- items:
- const: mrvl,mmp-uart
- enum:
- mrvl,mmp-uart
- spacemit,k1-uart
- const: intel,xscale-uart
- items:
- enum:

1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
View File

@ -31,6 +31,7 @@ properties:
- enum:
- canaan,k210-clint # Canaan Kendryte K210
- sifive,fu540-c000-clint # SiFive FU540
- spacemit,k1-clint # SpacemiT K1
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100

9
MAINTAINERS
View File

@ -20188,6 +20188,15 @@ F: drivers/perf/riscv_pmu.c
F: drivers/perf/riscv_pmu_legacy.c
F: drivers/perf/riscv_pmu_sbi.c
RISC-V SPACEMIT SoC Support
M: Yixun Lan <dlan@gentoo.org>
L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/spacemit-com/linux
F: arch/riscv/boot/dts/spacemit/
N: spacemit
K: spacemit
RISC-V THEAD SoC SUPPORT
M: Drew Fustini <drew@pdp7.com>
M: Guo Ren <guoren@kernel.org>

5
arch/riscv/Kconfig.socs
View File

@ -24,6 +24,11 @@ config ARCH_SOPHGO
help
This enables support for Sophgo SoC platform hardware.
config ARCH_SPACEMIT
bool "SpacemiT SoCs"
help
This enables support for SpacemiT SoC platform hardware.
config ARCH_STARFIVE
def_bool SOC_STARFIVE

1
arch/riscv/boot/dts/Makefile
View File

@ -5,6 +5,7 @@ subdir-y += microchip
subdir-y += renesas
subdir-y += sifive
subdir-y += sophgo
subdir-y += spacemit
subdir-y += starfive
subdir-y += thead

2
arch/riscv/boot/dts/spacemit/Makefile Normal file
View File

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb

26
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
*/
#include "k1.dtsi"
#include "k1-pinctrl.dtsi"
/ {
model = "Banana Pi BPI-F3";
compatible = "bananapi,bpi-f3", "spacemit,k1";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};

20
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
*/
#include <dt-bindings/gpio/gpio.h>
#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
&pinctrl {
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {
pinmux = <K1_PADCONF(68, 2)>,
<K1_PADCONF(69, 2)>;
bias-pull-up = <0>;
drive-strength = <32>;
};
};
};

452
arch/riscv/boot/dts/spacemit/k1.dtsi Normal file
View File

@ -0,0 +1,452 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "SpacemiT K1";
compatible = "spacemit,k1";
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <24000000>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_0>;
};
core1 {
cpu = <&cpu_1>;
};
core2 {
cpu = <&cpu_2>;
};
core3 {
cpu = <&cpu_3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_4>;
};
core1 {
cpu = <&cpu_5>;
};
core2 {
cpu = <&cpu_6>;
};
core3 {
cpu = <&cpu_7>;
};
};
};
cpu_0: cpu@0 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster0_l2_cache>;
mmu-type = "riscv,sv39";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu_1: cpu@1 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <1>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster0_l2_cache>;
mmu-type = "riscv,sv39";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu_2: cpu@2 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <2>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster0_l2_cache>;
mmu-type = "riscv,sv39";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu_3: cpu@3 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <3>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster0_l2_cache>;
mmu-type = "riscv,sv39";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu_4: cpu@4 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <4>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster1_l2_cache>;
mmu-type = "riscv,sv39";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu_5: cpu@5 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <5>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster1_l2_cache>;
mmu-type = "riscv,sv39";
cpu5_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu_6: cpu@6 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <6>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster1_l2_cache>;
mmu-type = "riscv,sv39";
cpu6_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu_7: cpu@7 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <7>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <128>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <128>;
next-level-cache = <&cluster1_l2_cache>;
mmu-type = "riscv,sv39";
cpu7_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <512>;
cache-unified;
};
cluster1_l2_cache: l2-cache1 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <512>;
cache-unified;
};
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
uart0: serial@d4017000 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
interrupts = <42>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@d4017100 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017100 0x0 0x100>;
interrupts = <44>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@d4017200 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017200 0x0 0x100>;
interrupts = <45>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@d4017300 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017300 0x0 0x100>;
interrupts = <46>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart5: serial@d4017400 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017400 0x0 0x100>;
interrupts = <47>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart6: serial@d4017500 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017500 0x0 0x100>;
interrupts = <48>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart7: serial@d4017600 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017600 0x0 0x100>;
interrupts = <49>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart8: serial@d4017700 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017700 0x0 0x100>;
interrupts = <50>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart9: serial@d4017800 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017800 0x0 0x100>;
interrupts = <51>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k1-pinctrl";
reg = <0x0 0xd401e000 0x0 0x400>;
};
plic: interrupt-controller@e0000000 {
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
reg = <0x0 0xe0000000 0x0 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>,
<&cpu5_intc 11>, <&cpu5_intc 9>,
<&cpu6_intc 11>, <&cpu6_intc 9>,
<&cpu7_intc 11>, <&cpu7_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
riscv,ndev = <159>;
};
clint: timer@e4000000 {
compatible = "spacemit,k1-clint", "sifive,clint0";
reg = <0x0 0xe4000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>,
<&cpu4_intc 3>, <&cpu4_intc 7>,
<&cpu5_intc 3>, <&cpu5_intc 7>,
<&cpu6_intc 3>, <&cpu6_intc 7>,
<&cpu7_intc 3>, <&cpu7_intc 7>;
};
sec_uart1: serial@f0612000 {
compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xf0612000 0x0 0x100>;
interrupts = <43>;
clock-frequency = <14857000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "reserved"; /* for TEE usage */
};
};
};

1
arch/riscv/configs/defconfig
View File

@ -30,6 +30,7 @@ CONFIG_ARCH_MICROCHIP=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_SIFIVE=y
CONFIG_ARCH_SOPHGO=y
CONFIG_ARCH_SPACEMIT=y
CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_THEAD=y