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RISC-V: Add Ssccfg extension CSR definition

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This adds the scountinhibit CSR definition and S-mode accessible hpmevent
bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop
counters directly from S-mode without invoking SBI calls to M-mode. It is
also used to figure out the counters delegated to S-mode by the M-mode as
well.

Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
Tested-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
[pjw@kernel.org: fixed subject typo]
Link: https://patch.msgid.link/20260807-counter_delegation-v9-8-58658104e487@meta.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Kaiwen Xue 2026-08-07 19:24:31 -06:00 committed by Paul Walmsley
parent 1c40a2d06d
commit 05e44c11f6
1 changed files with 18 additions and 0 deletions
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18
arch/riscv/include/asm/csr.h
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@ -241,6 +241,23 @@
#define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
#define SMSTATEEN0_SSTATEEN0_SHIFT 63
#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */
#define HPMEVENT_OF (BIT_ULL(63))
#define HPMEVENT_MINH (BIT_ULL(62))
#define HPMEVENT_SINH (BIT_ULL(61))
#define HPMEVENT_UINH (BIT_ULL(60))
#define HPMEVENT_VSINH (BIT_ULL(59))
#define HPMEVENT_VUINH (BIT_ULL(58))
#ifndef CONFIG_64BIT
#define HPMEVENTH_OF (BIT(31))
#define HPMEVENTH_MINH (BIT(30))
#define HPMEVENTH_SINH (BIT(29))
#define HPMEVENTH_UINH (BIT(28))
#define HPMEVENTH_VSINH (BIT(27))
#define HPMEVENTH_VUINH (BIT(26))
#endif
#define SISELECT_SSCCFG_BASE 0x40
/* mseccfg bits */
#define MSECCFG_PMM ENVCFG_PMM
@ -322,6 +339,7 @@
#define CSR_SCOUNTEREN 0x106
#define CSR_SENVCFG 0x10a
#define CSR_SSTATEEN0 0x10c
#define CSR_SCOUNTINHIBIT 0x120
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142