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by Qualcomm churning out new SoCs that need clk drivers. Looking beyond the sheer amount of lines of mostly data there we have a clk nexus DT binding change in the core clk framework and a driver core patch to add a subsys driver macro. The clock nexus support is useful for devices that map clks internally or for connectors on a board that route clock signals to another board. I suspect the use of this will expand in the future, so we have unit tests to make sure it doesn't break. The driver core change adds subsys_driver() and subsys_platform_driver() so we can register early drivers without open-coding that all (module_platform_driver() is at device initcall level so it isn't be used). Beyond the core framework bits we have lots of changes all over the tree to initialize 'struct clk_init_data'. The potential risk here is that someone forgets to initialize all the members of that structure and either the clk flags cause weird behavior later on or the parents are pointing at junk and the clk is orphaned forever. The patches just initialize the thing with zeroes to be safe. Longer term we should probably move this struct out of 'struct clk_hw' and pass it during clk registration time. That's a much bigger change and would require restructuring entire drivers that rely on the pointer being there. Finally, we have the usual fixes like calculation updates for dividers, handling error paths during clk registration, or fixing clk data now that drivers are using them. Those patches are dwarfed by the amount of new SoC support and only affect those SoCs and the consumers of those clks. Overall I'm more concerned the clk_init_data patches are going to expose some latent bugs that we didn't notice before because something was relying on clks being orphaned and now they're not. Core: - subsys_driver() / subsys_platform_driver() macros - Clock nexus DT binding support (with KUnit tests) - Spread-spectrum configuration validation - Fully initialize struct clk_init_data across many drivers New Drivers: - Anlogic DR1V90 CRU - ZTE zx297520v3 top, matrix, and LSP clocks - Samsung Exynos5515 and ACPM driver extended to Exynos850. - Qualcomm Eliza camera, camera-BIST, GPU, and video clks - Qualcomm Hawi / Maili camera and GPU controllers - Qualcomm Kuno global, RPMh - Qualcomm MSM8952 global, RPM - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets - Qualcomm IPQ5210 / IPQ9650 network clocks - i.MX93 350 MHz fractional-N GP-PLL for display - i.MX pll14xx spread-spectrum clock generation - Amlogic A9 SCMI clock controller - Allwinner single-divider "update bit" support - EN7523 Serdes port selection -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmri0R4UHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSWcAA//YrAnklSwDggOqJ3FwYZ8DHwXfcjU LQO4guUzlfNl3Lq4js1av5XetKtHk7ndtDxhbP6kLgFIZ+b2LbkPDEUOlxiPZ/47 MjrveKqgXgEVk6yAl1S8HpmL0BMSO+GZsr61Mcha3kjEUfgen4cZDGzETgyaxniW cqIrP6IRa/Z60c6IydRyK+kN/317TGp/VKPcXudtecey5FB+WlpaUQV9ntiOGBZZ 6icxy2O76v31XU/HJnb+IjTZ0Jc449rBDE+/T12OvoZ1z1Lv59mRgxJgZ0BwdMOP PoqTXLq6hby1IH37pCjSEp2X9qVhMsT9I40HM/Nn5uPZIvlDk6mZ4GXh0/sWZqC/ yYaf9gVouORSKV3DTMSD/njtsNKANoo/aj08Gxfr+hJHrA/7ohehntpeKobWlk9K X+0uzT0N1h6PgqlmDHDv0MvYYzUnNif1PRuN+0JFrpvf5Y1cc6jCKdapYVvQtr6i NzOs7XG1IbigWPlccUTl3hn0Bs15dLhOVUrWo1c9aPF4vkGpPtyHib8nLdCerbuP 7mICMzZ3PM76l9rl7VvO8wLNvBHBa+8f90jXE9Zz/0oyAj0fIdrNsXL6Nu+5usDA zT8T5Z2PfGgkx6TsftRmk0SZErROG0YakGRstSSSTYytHig0+JezVAH7NY26z7Dz Vcft0XmRGbL1jbU= =Vb8R -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Here's the clk changes for the merge window which is dominated in the diffstat by Qualcomm churning out new SoCs that need clk drivers. Looking beyond the sheer amount of lines of mostly data there we have a clk nexus DT binding change in the core clk framework and a driver core patch to add a subsys driver macro. The clock nexus support is useful for devices that map clks internally or for connectors on a board that route clock signals to another board. I suspect the use of this will expand in the future, so we have unit tests to make sure it doesn't break. The driver core change adds subsys_driver() and subsys_platform_driver() so we can register early drivers without open-coding that all (module_platform_driver() is at device initcall level so it isn't be used). Beyond the core framework bits we have lots of changes all over the tree to initialize 'struct clk_init_data'. The potential risk here is that someone forgets to initialize all the members of that structure and either the clk flags cause weird behavior later on or the parents are pointing at junk and the clk is orphaned forever. The patches just initialize the thing with zeroes to be safe. Longer term we should probably move this struct out of 'struct clk_hw' and pass it during clk registration time. That's a much bigger change and would require restructuring entire drivers that rely on the pointer being there. Finally, we have the usual fixes like calculation updates for dividers, handling error paths during clk registration, or fixing clk data now that drivers are using them. Those patches are dwarfed by the amount of new SoC support and only affect those SoCs and the consumers of those clks. Overall I'm more concerned the clk_init_data patches are going to expose some latent bugs that we didn't notice before because something was relying on clks being orphaned and now they're not. Core: - subsys_driver() / subsys_platform_driver() macros - Clock nexus DT binding support (with KUnit tests) - Spread-spectrum configuration validation - Fully initialize struct clk_init_data across many drivers New Drivers: - Anlogic DR1V90 CRU - ZTE zx297520v3 top, matrix, and LSP clocks - Samsung Exynos5515 and ACPM driver extended to Exynos850. - Qualcomm Eliza camera, camera-BIST, GPU, and video clks - Qualcomm Hawi / Maili camera and GPU controllers - Qualcomm Kuno global, RPMh - Qualcomm MSM8952 global, RPM - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets - Qualcomm IPQ5210 / IPQ9650 network clocks - i.MX93 350 MHz fractional-N GP-PLL for display - i.MX pll14xx spread-spectrum clock generation - Amlogic A9 SCMI clock controller - Allwinner single-divider "update bit" support - EN7523 Serdes port selection" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits) clk: imx: pll14xx: support spread spectrum clock generation clk: cdce925: Size the PLL child name buffer for any int clk: stm32: fix clock array size for STM32MP21 dt-bindings: clock: Convert HiSilicon clocks to DT schema clk: lmk04832: Handle reset GPIO lookup errors dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional clk: tegra: bpmp: remove kcalloc clk: mmp2-audio: add missing PM_CLK dependency clk: zte: Introduce a driver for zx297520v3 LSP clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Add zx PLL support infrastructure clk: zte: Add regmap-based clocks clk: zte: Add Clock registration infrastructure dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define ... |
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| clk.rs | ||
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