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The driver polls CFG_RDY for 0 as notification that the endpoint has finished teardown and a new session can start safely. After a bad bitstream that poll can time out: CFG_RDY may stay stuck when HIP_CLK_SEL=0 if the device has already left usermode before the poll. Retrying teardown alone is not enough. Exit CvP mode and switch the HIP clock that feeds CFG_RDY so CVP_STATUS becomes responsive again, then try the teardown once more. Introduce altera_cvp_recovery() to wrap this cleanup and single retry. Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/20260923053233.10890-3-muhammad.nazim.amirul.nazle.asmade@altera.com Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com> |
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| .. | ||
| tests | ||
| altera-cvp.c | ||
| altera-fpga2sdram.c | ||
| altera-freeze-bridge.c | ||
| altera-hps2fpga.c | ||
| altera-pr-ip-core-plat.c | ||
| altera-pr-ip-core.c | ||
| altera-ps-spi.c | ||
| dfl-afu-dma-region.c | ||
| dfl-afu-error.c | ||
| dfl-afu-main.c | ||
| dfl-afu-region.c | ||
| dfl-afu.h | ||
| dfl-fme-br.c | ||
| dfl-fme-error.c | ||
| dfl-fme-main.c | ||
| dfl-fme-mgr.c | ||
| dfl-fme-perf.c | ||
| dfl-fme-pr.c | ||
| dfl-fme-pr.h | ||
| dfl-fme-region.c | ||
| dfl-fme.h | ||
| dfl-n3000-nios.c | ||
| dfl-pci.c | ||
| dfl.c | ||
| dfl.h | ||
| efinix-spi.c | ||
| fpga-bridge.c | ||
| fpga-mgr.c | ||
| fpga-region.c | ||
| ice40-spi.c | ||
| intel-m10-bmc-sec-update.c | ||
| Kconfig | ||
| lattice-sysconfig-spi.c | ||
| lattice-sysconfig.c | ||
| lattice-sysconfig.h | ||
| machxo2-spi.c | ||
| Makefile | ||
| microchip-spi.c | ||
| of-fpga-region.c | ||
| socfpga-a10.c | ||
| socfpga.c | ||
| stratix10-soc.c | ||
| ts73xx-fpga.c | ||
| versal-fpga.c | ||
| xilinx-core.c | ||
| xilinx-core.h | ||
| xilinx-pr-decoupler.c | ||
| xilinx-selectmap.c | ||
| xilinx-spi.c | ||
| zynq-fpga.c | ||
| zynqmp-fpga.c | ||