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486a70ef84
The comment in the mtk_phy_tmds_clk_ratio() function clearly and
correctly explains that the TMDS ratio has to be 1/10 for data
rates under 3.4Gbps, and 1/40 over that.
Unfortunately though, the TXC_DIV register setting was wrong, as
in value 3 means to divide by 8 and, in order to achieve the in
spec 1/40 (tmds) data rate, this has to divide by 4 instead!
Add definitions for the TXC_DIV register values clearly explaining
the meanings (DIV2, DIV4, DIV8), and program the correct, DIV 4,
value to the register in mtk_phy_tmds_clk_ratio().
This fixes out of spec clocking and, with this change, SoCs using
the MT8195 class HDMI PHYs can now successfully be configured to
output 3840x2160@60Hz over HDMI.
Fixes:
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|---|---|---|
| .. | ||
| allwinner | ||
| amlogic | ||
| apple | ||
| axiado | ||
| broadcom | ||
| cadence | ||
| canaan | ||
| eswin | ||
| freescale | ||
| hisilicon | ||
| ingenic | ||
| intel | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| microchip | ||
| motorola | ||
| mscc | ||
| nuvoton | ||
| qualcomm | ||
| ralink | ||
| realtek | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| socionext | ||
| sophgo | ||
| spacemit | ||
| st | ||
| starfive | ||
| sunplus | ||
| tegra | ||
| ti | ||
| xilinx | ||
| Kconfig | ||
| Makefile | ||
| phy-airoha-pcie-regs.h | ||
| phy-airoha-pcie.c | ||
| phy-can-transceiver.c | ||
| phy-common-props-test.c | ||
| phy-common-props.c | ||
| phy-core-mipi-dphy.c | ||
| phy-core.c | ||
| phy-econet-pcie.c | ||
| phy-eyeq5-eth.c | ||
| phy-google-usb.c | ||
| phy-lgm-usb.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-nxp-ptn3222.c | ||
| phy-nxp-tja1145.c | ||
| phy-pistachio-usb.c | ||
| phy-snps-eusb2.c | ||
| phy-xgene.c | ||