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a0e0c2f8c5
Instead of grouping several different reset lines into one composite reset, decouple them to individual ones which make it more aligned with underlying hardware. And for DWC USB driver, it will match well with the number of the reset property in the DT bindings. The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. Also three reset lines each for UCIE and RCPU block. As an agreement with maintainer, the reset IDs has been rearranged as contiguous number but keep most part unchanged to avoid break patches which already sent to mailing list. The changes of DT binding header file and reset driver are merged together as one single commit to avoid git-bisect breakage. Fixes: |
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| arm | ||
| ata | ||
| bus | ||
| clock | ||
| display | ||
| dma | ||
| firmware | ||
| gce | ||
| gpio | ||
| i2c | ||
| i3c | ||
| iio | ||
| input | ||
| interconnect | ||
| interrupt-controller | ||
| leds | ||
| mailbox | ||
| media | ||
| memory | ||
| mfd | ||
| mips | ||
| mux | ||
| net | ||
| nvmem | ||
| phy | ||
| pinctrl | ||
| pmu | ||
| power | ||
| pwm | ||
| regulator | ||
| reset | ||
| soc | ||
| sound | ||
| spmi | ||
| thermal | ||
| usb | ||
| watchdog | ||