linux/arch
Shaohua Li ffebdff74f x86/apic: Serialize LVTT and TSC_DEADLINE writes
commit 5d7c631d92 upstream.

The APIC LVTT register is MMIO mapped but the TSC_DEADLINE register is an
MSR. The write to the TSC_DEADLINE MSR is not serializing, so it's not
guaranteed that the write to LVTT has reached the APIC before the
TSC_DEADLINE MSR is written. In such a case the write to the MSR is
ignored and as a consequence the local timer interrupt never fires.

The SDM decribes this issue for xAPIC and x2APIC modes. The
serialization methods recommended by the SDM differ.

xAPIC:
 "1. Memory-mapped write to LVT Timer Register, setting bits 18:17 to 10b.
  2. WRMSR to the IA32_TSC_DEADLINE MSR a value much larger than current time-stamp counter.
  3. If RDMSR of the IA32_TSC_DEADLINE MSR returns zero, go to step 2.
  4. WRMSR to the IA32_TSC_DEADLINE MSR the desired deadline."

x2APIC:
 "To allow for efficient access to the APIC registers in x2APIC mode,
  the serializing semantics of WRMSR are relaxed when writing to the
  APIC registers. Thus, system software should not use 'WRMSR to APIC
  registers in x2APIC mode' as a serializing instruction. Read and write
  accesses to the APIC registers will occur in program order. A WRMSR to
  an APIC register may complete before all preceding stores are globally
  visible; software can prevent this by inserting a serializing
  instruction, an SFENCE, or an MFENCE before the WRMSR."

The xAPIC method is to just wait for the memory mapped write to hit
the LVTT by checking whether the MSR write has reached the hardware.
There is no reason why a proper MFENCE after the memory mapped write would
not do the same. Andi Kleen confirmed that MFENCE is sufficient for the
xAPIC case as well.

Issue MFENCE before writing to the TSC_DEADLINE MSR. This can be done
unconditionally as all CPUs which have TSC_DEADLINE also have MFENCE
support.

[ tglx: Massaged the changelog ]

Signed-off-by: Shaohua Li <shli@fb.com>
Reviewed-by: Ingo Molnar <mingo@kernel.org>
Cc: <Kernel-team@fb.com>
Cc: <lenb@kernel.org>
Cc: <fenghua.yu@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/20150909041352.GA2059853@devbig257.prn2.facebook.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-10-22 14:37:49 -07:00
..
alpha vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
arc ARC: make sure instruction_pointer() returns unsigned value 2015-08-10 12:20:30 -07:00
arm ARM: 8429/1: disable GCC SRA optimization 2015-10-22 14:37:49 -07:00
arm64 arm64: head.S: initialise mdcr_el2 in el2_setup 2015-10-01 12:07:29 +02:00
avr32 vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
blackfin blackfin updates for Linux 3.10 2013-05-10 07:21:16 -07:00
c6x C6x: time: Ensure consistency in __init 2015-05-06 21:56:28 +02:00
cris vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
frv vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
h8300 We get rid of the general module prefix confusion with a binary config option, 2013-05-05 10:58:06 -07:00
hexagon arch: mm: pass userspace fault flag to generic fault handler 2014-11-21 09:22:56 -08:00
ia64 vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
m32r vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
m68k vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
metag vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
microblaze vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
mips signal: fix information leak in copy_siginfo_from_user32 2015-08-16 20:51:42 -07:00
mn10300 vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
openrisc vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
parisc parisc: Filter out spurious interrupts in PA-RISC irq handler 2015-10-01 12:07:32 +02:00
powerpc powerpc/rtas: Introduce rtas_get_sensor_fast() for IRQ handlers 2015-10-01 12:07:30 +02:00
s390 s390/sclp: clear upper register halves in _sclp_print_early 2015-08-10 12:20:29 -07:00
score vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
sh nosave: consolidate __nosave_{begin,end} in <asm/sections.h> 2015-05-06 21:56:28 +02:00
sparc sparc64: Fix userspace FPU register corruptions. 2015-08-16 20:51:38 -07:00
tile tile: use free_bootmem_late() for initrd 2015-08-10 12:20:30 -07:00
um vm: add VM_FAULT_SIGSEGV handling support 2015-04-29 10:34:00 +02:00
unicore32 nosave: consolidate __nosave_{begin,end} in <asm/sections.h> 2015-05-06 21:56:28 +02:00
x86 x86/apic: Serialize LVTT and TSC_DEADLINE writes 2015-10-22 14:37:49 -07:00
xtensa xtensa: don't use echo -e needlessly 2015-09-21 10:00:10 -07:00
.gitignore
Kconfig microblaze: fix clone syscall 2013-08-20 08:43:02 -07:00