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The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@starfivetech.com
50 lines
1.0 KiB
YAML
50 lines
1.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/starfive,jhb100-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive External Interrupt Controller
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description:
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StarFive SoC JHB100 contain a external interrupt controller. It can be used
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to handle high-level input interrupt signals. It also send the output
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interrupt signal to RISC-V PLIC.
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maintainers:
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- Changhuang Liang <changhuang.liang@starfivetech.com>
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properties:
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compatible:
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const: starfive,jhb100-intc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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additionalProperties: false
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examples:
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- |
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interrupt-controller@12260000 {
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compatible = "starfive,jhb100-intc";
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reg = <0x12260000 0x10000>;
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interrupts = <45>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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