Zheng Yang f8fbbc4520 drm: bridge: dw-hdmi: introduce mpll_cfg_420 ... RK3368/RK3399 mpll input clock rate is twice of mpll output in YCBCR420 mode. This patch introduce mpll_cfg_420 to get the platform YCBCR420 phy setting. If mpll_cfg_420 is not exist, use mpll_cfg. Change-Id: I7910a75394cf371a8008f8a83e3ab9ec14e9a68a Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>		2017-12-11 15:27:58 +08:00
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arm	MALI: utgard: to adapt legacy GPU dts node format for mali_device befor r5p0	2017-12-04 17:58:27 +08:00
drm	drm: bridge: dw-hdmi: introduce mpll_cfg_420	2017-12-11 15:27:58 +08:00
host1x	rk: revert to v3.10	2015-11-11 15:57:28 +08:00
ipu-v3	drm/imx: Match imx-ipuv3-crtc components using device node in platform data	2016-06-07 18:14:37 -07:00
rogue	RK3368 GPU version: Rogue L 0.22	2015-08-17 14:12:00 +08:00
rogue_m	GPU: Rogue_M: update to 1.31_2 version & support gpu pd.	2016-01-18 19:04:28 +08:00
vga	vgaarb: fix signal handling in vga_get()	2015-12-11 14:04:44 +10:00
Makefile	MALI: add midgard src dir	2016-03-09 16:51:03 +08:00