linux/drivers/gpu
Maxime Ripard f8b13d9bcc
drm/vc4: hvs: Make sure our channel is reset
In order to clear our intermediate FIFOs that might end up with a stale
pixel, let's make sure our FIFO channel is reset every time our channel is
setup.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b34c562b36177c758dd2e9d84bceb07689bfbe05.1599120059.git-series.maxime@cerno.tech
2020-09-07 18:03:44 +02:00
..
drm drm/vc4: hvs: Make sure our channel is reset 2020-09-07 18:03:44 +02:00
host1x gpu: host1x: debug: Dump push buffer state 2020-07-17 16:06:14 +02:00
ipu-v3 gpu: ipu-v3: image-convert: Wait for all EOFs before completing a tile 2020-07-20 15:16:05 +02:00
trace
vga vgaarb: mark vga_tryget static 2020-08-01 11:28:17 +02:00
Makefile