mirror of
https://github.com/torvalds/linux.git
synced 2026-09-20 09:40:02 +02:00
f8020dfb31
So far all RK3588 boards use fully aggregated PCIe. CM3588 is one
of the few boards using this feature and apparently it is broken.
The PHY offers the following mapping options:
port 0 lane 0 - always mapped to controller 0 (4L)
port 0 lane 1 - to controller 0 or 2 (1L0)
port 1 lane 0 - to controller 0 or 1 (2L)
port 1 lane 1 - to controller 0, 1 or 3 (1L1)
The data-lanes DT property maps these as follows:
0 = no controller (unsupported by the HW)
1 = 4L
2 = 2L
3 = 1L0
4 = 1L1
That allows the following configurations with first column being the
mainline data-lane mapping, second column being the downstream name,
third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register
values and final column being the user visible lane setup:
<1 1 1 1> = AGGREG = [4 0] = x4 (aggregation)
<1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.)
<1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0)
<1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1)
<1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports)
The driver currently does not program PHP_GRF_PCIESEL correctly, which
is fixed by this patch. As a side-effect the new logic is much simpler
than the old logic.
Fixes:
|
||
|---|---|---|
| .. | ||
| allwinner | ||
| amlogic | ||
| broadcom | ||
| cadence | ||
| freescale | ||
| hisilicon | ||
| ingenic | ||
| intel | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| microchip | ||
| motorola | ||
| mscc | ||
| qualcomm | ||
| ralink | ||
| realtek | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| socionext | ||
| st | ||
| starfive | ||
| sunplus | ||
| tegra | ||
| ti | ||
| xilinx | ||
| Kconfig | ||
| Makefile | ||
| phy-can-transceiver.c | ||
| phy-core-mipi-dphy.c | ||
| phy-core.c | ||
| phy-lgm-usb.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||