linux/arch/powerpc/include/asm/nohash
Christophe Leroy f76c8f6d25 powerpc/8xx: Add function to set pinned TLBs
Pinned TLBs cannot be modified when the MMU is enabled.

Create a function to rewrite the pinned TLB entries with MMU off.

To set pinned TLB, we have to turn off MMU, disable pinning,
do a TLB flush (Either with tlbie and tlbia) then reprogam
the TLB entries, enable pinning and turn on MMU.

If using tlbie, it cleared entries in both instruction and data
TLB regardless whether pinning is disabled or not.
If using tlbia, it clears all entries of the TLB which has
disabled pinning.

To make it easy, just clear all entries in both TLBs, and
reprogram them.

The function takes two arguments, the top of the memory to
consider and whether data is RO under _sinittext.
When DEBUG_PAGEALLOC is set, the top is the end of kernel rodata.
Otherwise, that's the top of physical RAM.

Everything below _sinittext is set RX, over _sinittext that's RW.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c17806014bb1c06513ad1e1d510faea31984b177.1589866984.git.christophe.leroy@csgroup.eu
2020-05-26 22:22:21 +10:00
..
32 powerpc/8xx: Add function to set pinned TLBs 2020-05-26 22:22:21 +10:00
64 powerpc/mm: PTE_ATOMIC_UPDATES is only for 40x 2020-05-26 22:22:20 +10:00
hugetlb-book3e.h powerpc/mm: cleanup ifdef mess in add_huge_page_size() 2019-05-03 01:20:23 +10:00
mmu-book3e.h powerpc/fsl_booke/32: implement KASLR infrastructure 2019-11-13 19:27:40 +11:00
mmu.h powerpc/mm: get rid of nohash/32/mmu.h and nohash/64/mmu.h 2019-05-03 01:20:24 +10:00
pgalloc.h powerpc/mmu_gather: enable RCU_TABLE_FREE even for !SMP case 2020-02-04 03:05:25 +00:00
pgtable.h powerpc/8xx: Manage 512k huge pages as standard pages. 2020-05-26 22:22:21 +10:00
pte-book3e.h powerpc/64: only book3s/64 supports CONFIG_PPC_64K_PAGES 2019-05-03 01:20:23 +10:00
tlbflush.h powerpc: split asm/tlbflush.h 2018-07-30 22:48:21 +10:00