Charlene Liu f1fd8a9ac2 drm/amd/display: Correct sw cache timing to ensure dispclk ramping ... [why] Current driver will cache the dispclk right after send cmd to pmfw, but actual clock not reached yet. Change to only cache the dispclk setting after HW reached to the real clock. Also give some range as it might be in bypass clock setting. Reviewed-by: Yihan Zhu <yihan.zhu@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2025-09-23 10:32:20 -04:00
..
drm	drm/amd/display: Correct sw cache timing to ensure dispclk ramping	2025-09-23 10:32:20 -04:00
host1x
ipu-v3	gpu: ipu-v3: Switch to irq_find_mapping()	2025-05-16 21:06:12 +02:00
nova-core	DRM Rust changes for v6.18	2025-09-17 16:13:49 +10:00
trace	gpu/trace: make TRACE_GPU_MEM configurable	2025-07-08 09:34:47 -07:00
vga	vga_switcheroo: Use pci_is_display()	2025-07-17 15:30:13 -05:00
Makefile