Alvin Lee f0ec30549a drm/amd/display: Ensure populate uclk in bb construction ... [Description] - For some SKUs, the optimal DCFCLK for each UCLK is less than the smallest DCFCLK STA target due to low memory bandwidth. There is an assumption that the DCFCLK STA targets will always be less than one of the optimal DCFCLK values, but this is not true for SKUs that have low memory bandwidth. In this case we need to populate the optimal UCLK for each DCFCLK STA targets as the max UCLK freq. - Also fix a bug in DML where start_state is not assigned and used correctly. Reviewed-by: Samson Tam <samson.tam@amd.com> Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2024-01-15 18:35:39 -05:00
..
amdgpu_dm	drm/amd/display: Allow IPS2 during Replay	2024-01-15 18:35:37 -05:00
dc	drm/amd/display: Ensure populate uclk in bb construction	2024-01-15 18:35:39 -05:00
dmub	drm/amd/display: Add Replay IPS register for DMUB command table	2024-01-15 18:35:37 -05:00
include	drm/amd/display: To adjust dprefclk by down spread percentage	2024-01-09 15:43:53 -05:00
modules	drm/amd/display: Fix power_helpers.c codestyle	2024-01-05 16:10:44 -05:00
Kconfig	drm/amd/display: Allow building DC with clang on RISC-V	2023-07-21 16:52:25 -04:00
Makefile	drm/amd/display: Refactor OPTC into component folder	2023-11-29 16:49:01 -05:00
TODO