Suraj Kandpal eaed815ca3 drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency ... DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the symbol clock computed assuming 8b/10b encoding (link_rate / 10). For DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to be modified. DDI_CLK_VALFREQ does not have any functional impact on H/w, it only records the frequency S/w intends to set. Use intel_ddi_link_symbol_clock() to write the correct DDI clock in kHz Fixes: 5ec58d7149 ("drm/i915/lt_phy: Add .enable_clock hook on DDI") Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260811175844.2613721-4-suraj.kandpal@intel.com		2026-08-12 09:32:32 +05:30
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drm	drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency	2026-08-12 09:32:32 +05:30
host1x	gpu: host1x: Fix iommu_map_sgtable() return value check	2026-05-28 17:19:30 +02:00
ipu-v3
nova-core	drm-next for 7.2-rc1	2026-06-17 10:21:00 +01:00
tests
trace
vga	fbdev: Wrap fbcon updates from vga-switcheroo in helper	2026-06-09 16:00:11 +02:00
buddy.c	drm/buddy: Integrate lockdep annotations for gpu buddy manager	2026-05-08 19:16:19 +05:30
Kconfig
Makefile