Dave Stevenson 21c890ca8e drm/vc4: hdmi: Allow DBLCLK modes even if horz timing is odd. ... [ Upstream commit 1d11896596 ] The 2711 pixel valve can't produce odd horizontal timings, and checks were added to vc4_hdmi_encoder_atomic_check and vc4_hdmi_encoder_mode_valid to filter out/block selection of such modes. Modes with DRM_MODE_FLAG_DBLCLK double all the horizontal timing values before programming them into the PV. The PV values, therefore, can not be odd, and so the modes can be supported. Amend the filtering appropriately. Fixes: 57fb32e632 ("drm/vc4: hdmi: Block odd horizontal timings") Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20220127135116.298278-1-maxime@cerno.tech Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-02-16 12:54:24 +01:00
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Kconfig
Makefile
vc4_bo.c	drm/vc4: fix error code in vc4_create_object()	2021-12-01 09:19:04 +01:00
vc4_crtc.c	drm/vc4: crtc: Skip the TXP	2021-07-19 09:44:57 +02:00
vc4_debugfs.c
vc4_dpi.c
vc4_drv.c
vc4_drv.h	drm/vc4: fix argument ordering in vc4_crtc_get_margins()	2021-07-19 09:44:37 +02:00
vc4_dsi.c
vc4_fence.c
vc4_gem.c
vc4_hdmi_phy.c
vc4_hdmi_regs.h	drm/vc4: hdmi: Fix up CEC registers	2021-03-04 11:37:48 +01:00
vc4_hdmi.c	drm/vc4: hdmi: Allow DBLCLK modes even if horz timing is odd.	2022-02-16 12:54:24 +01:00
vc4_hdmi.h
vc4_hvs.c
vc4_irq.c
vc4_kms.c
vc4_packet.h
vc4_perfmon.c
vc4_plane.c	drm/vc4: hvs: Fix buffer overflow with the dlist handling	2021-02-17 11:02:25 +01:00
vc4_qpu_defines.h
vc4_regs.h
vc4_render_cl.c
vc4_trace_points.c
vc4_trace.h
vc4_txp.c	drm/vc4: txp: Properly set the possible_crtcs mask	2021-07-19 09:44:57 +02:00
vc4_v3d.c
vc4_validate_shaders.c
vc4_validate.c
vc4_vec.c