Nathan Chancellor e89c2e815e riscv: Handle zicsr/zifencei issues between clang and binutils ... There are two related issues that appear in certain combinations with clang and GNU binutils. The first occurs when a version of clang that supports zicsr or zifencei via '-march=' [1] (i.e, >= 17.x) is used in combination with a version of GNU binutils that do not recognize zicsr and zifencei in the '-march=' value (i.e., < 2.36): riscv64-linux-gnu-ld: -march=rv64i2p0_m2p0_a2p0_c2p0_zicsr2p0_zifencei2p0: Invalid or unknown z ISA extension: 'zifencei' riscv64-linux-gnu-ld: failed to merge target specific data of file fs/efivarfs/file.o riscv64-linux-gnu-ld: -march=rv64i2p0_m2p0_a2p0_c2p0_zicsr2p0_zifencei2p0: Invalid or unknown z ISA extension: 'zifencei' riscv64-linux-gnu-ld: failed to merge target specific data of file fs/efivarfs/super.o The second occurs when a version of clang that does not support zicsr or zifencei via '-march=' (i.e., <= 16.x) is used in combination with a version of GNU as that defaults to a newer ISA base spec, which requires specifying zicsr and zifencei in the '-march=' value explicitly (i.e, >= 2.38): ../arch/riscv/kernel/kexec_relocate.S: Assembler messages: ../arch/riscv/kernel/kexec_relocate.S:147: Error: unrecognized opcode `fence.i', extension `zifencei' required clang-12: error: assembler command failed with exit code 1 (use -v to see invocation) This is the same issue addressed by commit 6df2a016c0 ("riscv: fix build with binutils 2.38") (see [2] for additional information) but older versions of clang miss out on it because the cc-option check fails: clang-12: error: invalid arch name 'rv64imac_zicsr_zifencei', unsupported standard user-level extension 'zicsr' clang-12: error: invalid arch name 'rv64imac_zicsr_zifencei', unsupported standard user-level extension 'zicsr' To resolve the first issue, only attempt to add zicsr and zifencei to the march string when using the GNU assembler 2.38 or newer, which is when the default ISA spec was updated, requiring these extensions to be specified explicitly. LLVM implements an older version of the base specification for all currently released versions, so these instructions are available as part of the 'i' extension. If LLVM's implementation is updated in the future, a CONFIG_AS_IS_LLVM condition can be added to CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. To resolve the second issue, use version 2.2 of the base ISA spec when using an older version of clang that does not support zicsr or zifencei via '-march=', as that is the spec version most compatible with the one clang/LLVM implements and avoids the need to specify zicsr and zifencei explicitly due to still being a part of 'i'. [1]: 22e199e6af [2]: https://lore.kernel.org/ZAxT7T9Xy1Fo3d5W@aurel32.net/ Cc: stable@vger.kernel.org Link: https://github.com/ClangBuiltLinux/linux/issues/1808 Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230313-riscv-zicsr-zifencei-fiasco-v1-1-dd1b7840a551@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-03-23 12:52:49 -07:00
..
boot	SoC: DT changes for 6.3	2023-02-20 15:49:56 -08:00
configs	riscv: defconfig: Enable the Allwinner D1 platform and drivers	2023-01-27 23:10:08 +01:00
errata	RISC-V: fix taking the text_mutex twice during sifive errata patching	2023-03-07 12:39:12 -08:00
include	riscv: mm: Fix incorrect ASID argument when flushing TLB	2023-03-21 15:55:19 -07:00
kernel	RISC-V: Don't check text_mutex during stop_machine	2023-03-09 14:58:51 -08:00
kvm	ARM:	2023-02-25 11:30:21 -08:00
lib	riscv, lib: Fix Zbb strncmp	2023-02-28 18:42:38 -08:00
mm	riscv: mm: Fix incorrect ASID argument when flushing TLB	2023-03-21 15:55:19 -07:00
net	riscv, bpf: Add bpf trampoline support for RV64	2023-02-17 21:45:30 +01:00
purgatory	RISC-V: add infrastructure to allow different str* implementations	2023-01-31 11:43:23 -08:00
Kbuild	riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild	2022-06-01 22:26:32 -07:00
Kconfig	riscv: Handle zicsr/zifencei issues between clang and binutils	2023-03-23 12:52:49 -07:00
Kconfig.debug
Kconfig.erratas	drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores	2022-10-27 14:35:20 -07:00
Kconfig.socs	RISC-V Patches for the 6.3 Merge Window, Part 1	2023-02-25 11:14:08 -08:00
Makefile	riscv: Handle zicsr/zifencei issues between clang and binutils	2023-03-23 12:52:49 -07:00