Chris Wilson e67d01d849 drm/i915/gt: Flush xcs before tgl breadcrumbs ... In a simple test case that writes to scratch and then busy-waits for the batch to be signaled, we observe that the signal is before the write is posted. That is bad news. Splitting the flush + write_dword into two separate flush_dw prevents the issue from being reproduced, we can presume the post-sync op is not so post-sync. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/216 Testcase: igt/gem_exec_fence/parallel Testcase: igt/i915_selftest/live/gt_timelines Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: stable@vger.kernel.org Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201102221057.29626-2-chris@chris-wilson.co.uk (cherry picked from commit 09212e81e5) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>		2020-11-03 19:22:42 -05:00
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drm	drm/i915/gt: Flush xcs before tgl breadcrumbs	2020-11-03 19:22:42 -05:00
host1x	drm next for 5.10-rc1	2020-10-15 10:46:16 -07:00
ipu-v3	treewide: Use fallthrough pseudo-keyword	2020-08-23 17:36:59 -05:00
trace
vga	vgaarb: mark vga_tryget static	2020-08-01 11:28:17 +02:00
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