mirror of
https://github.com/torvalds/linux.git
synced 2026-06-08 14:42:37 +02:00
fe1b05dabd
The VOP DCLK is used to generate panel clocks. For veyron, we have decided to permanently assign vop0 for use with HDMI and vop1 for use with eDP. Furthermore, to allow us to generate a wide range of precise pixel clocks, we will be dedicating the NPLL exclusively for use as the parent clock for VOP0/HDMI. To implement the exclusive assignment of NPLL in the kernel, we remove the NPLL entry from all clock muxes that would otherwise be able to select it (such as vop1). For vop0, we remove all choices *except* NPLL. Before booting the kernel, the bios will configure vop0 and vop1 as it sees fit - potentially assigning NPLL to vop1 and some other PLL to vop0. Thus, at boot it is possible that from the kernel's perspective, these clocks are orphans. To fix this, we explicitly assign their clock parents to ensure that they are properly parented no matter what state they are when the kernel boots. Change-Id: Iafe301abcbf211246fda66519cea5fc946af97ee Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> |
||
|---|---|---|
| .. | ||
| alpha | ||
| arc | ||
| arm | ||
| arm64 | ||
| avr32 | ||
| blackfin | ||
| c6x | ||
| cris | ||
| frv | ||
| h8300 | ||
| hexagon | ||
| ia64 | ||
| m32r | ||
| m68k | ||
| metag | ||
| microblaze | ||
| mips | ||
| mn10300 | ||
| nios2 | ||
| openrisc | ||
| parisc | ||
| powerpc | ||
| s390 | ||
| score | ||
| sh | ||
| sparc | ||
| tile | ||
| um | ||
| unicore32 | ||
| x86 | ||
| xtensa | ||
| .gitignore | ||
| Kconfig | ||