Tommaso Merciai 6913a61596 clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks ... Add support for the PLLDSI{0,1} clocks in the r9a09g047 CPG driver. Introduce CLK_PLLDSI{0,1} also, introduce the rzg3e_cpg_pll_dsi{0,1}_limits structures to describe the frequency constraints specific to the RZ/G3E SoC. On Renesas RZ/G3E: - PLLDSI0 maximum output frequency: 1218 MHz - PLLDSI1 maximum output frequency: 609 MHz These limits are enforced through the newly added RZG3E_CPG_PLL_DSI{0,1}_LIMITS(). Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://patch.msgid.link/d26ec5349b0eb7ddb7d244fc53d1111a8530328f.1775636898.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>		2026-05-04 14:03:08 +02:00
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analogbits-wrpll-cln28hpc.h
at91_pmc.h	ARM: at91: remove default values for PMC_PLL_ACR	2025-09-17 19:15:32 +02:00
clk-conf.h
davinci.h	clk: davinci: remove support for da830	2025-03-13 13:17:41 -07:00
imx.h
mxs.h
pxa.h	ARM: pxa: move clk register definitions to driver	2022-05-07 22:55:49 +02:00
renesas.h	clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks	2026-05-04 14:03:08 +02:00
samsung.h	ARM: s3c: remove s3c24xx specific hacks	2023-01-16 09:26:05 +01:00
spear.h	clk: spear: Move prototype to accessible header	2022-10-10 10:37:58 +02:00
sunxi-ng.h	clk: sunxi-ng: Add support for the sun6i RTC clocks	2022-03-23 19:58:38 +01:00
tegra.h	clk: tegra: Add stubs needed for compile testing	2021-10-05 19:08:11 +02:00
ti.h	clk: ti: dpll: convert from round_rate() to determine_rate()	2025-09-08 12:50:55 -04:00
zynq.h