Kever Yang df5f7115ff phy: rockchip: naneng-combophy: Set pcie to use T3-p1 ... T3-p1 with 650mV output voltage is the best signal via the test. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: I5c2bd3ab0c235f3079925a03a59c419ad37da485		2022-08-09 19:31:40 +08:00
..
allwinner
amlogic
broadcom	phy: usb: Leave some clocks running during suspend	2022-02-23 12:01:05 +01:00
cadence
freescale
hisilicon
intel	phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP	2021-07-20 16:05:46 +02:00
lantiq
marvell
mediatek
motorola
mscc
qualcomm	phy: qcom-snps: Correct the FSEL_MASK	2021-11-18 14:04:20 +01:00
ralink
renesas
rockchip	phy: rockchip: naneng-combophy: Set pcie to use T3-p1	2022-08-09 19:31:40 +08:00
samsung
socionext	phy: uniphier-usb3ss: fix unintended writing zeros to PHY register	2022-01-27 10:54:08 +01:00
st
tegra
ti	phy: ti: Fix missing sentinel for clk_div_table	2022-02-16 12:54:30 +01:00
xilinx	phy: xilinx: zynqmp: Fix bus width setting for SGMII	2022-02-16 12:54:23 +01:00
Kconfig
Makefile
phy-core-mipi-dphy.c	phy: dphy: Correct lpx parameter and its derivatives(ta_{get,go,sure})	2022-04-08 14:40:24 +02:00
phy-core.c
phy-lgm-usb.c
phy-lpc18xx-usb-otg.c
phy-pistachio-usb.c
phy-xgene.c