Algea Cao 66d9343d63 phy: rockchip-samsung-hdptx-hdmi: FRL 8Gbps * 4 lanes mode use pll cascade mode ... Vendor suggest FRL 8G * 4 lanes mode use ROPLL/LCPLL cascade mode. ROPLL ref clock is from LCPLL. Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: If40f4ec55e44f1e53995cf932c68fa374662d636		2022-11-09 14:34:05 +08:00
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allwinner
amlogic
broadcom	phy: usb: Leave some clocks running during suspend	2022-02-23 12:01:05 +01:00
cadence
freescale
hisilicon
intel
lantiq
marvell
mediatek
motorola
mscc
qualcomm
ralink
renesas
rockchip	phy: rockchip-samsung-hdptx-hdmi: FRL 8Gbps * 4 lanes mode use pll cascade mode	2022-11-09 14:34:05 +08:00
samsung
socionext	phy: uniphier-usb3ss: fix unintended writing zeros to PHY register	2022-01-27 10:54:08 +01:00
st
tegra
ti	phy: ti: Fix missing sentinel for clk_div_table	2022-02-16 12:54:30 +01:00
xilinx	phy: xilinx: zynqmp: Fix bus width setting for SGMII	2022-02-16 12:54:23 +01:00
Kconfig
Makefile
phy-core-mipi-dphy.c	phy: dphy: Correct lpx parameter and its derivatives(ta_{get,go,sure})	2022-04-08 14:40:24 +02:00
phy-core.c
phy-lgm-usb.c
phy-lpc18xx-usb-otg.c
phy-pistachio-usb.c
phy-xgene.c