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f12659ebfa
PLL 491520000 for audio samplerate:
8000
16000
24000
32000
48000
64000
96000
128000
192000
ppm ranges [-1000 : +976] for clk compensation
PLL 496742400 for audio samplerate:
11025
22050
44100
88200
176400
ppm ranges [-1000 : +1000] for clk compensation
e.g. UAC with 48000 SR + UVC:
&cru {
assigned-clocks =
<&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
<&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
<&cru PLL_HPLL>, <&cru ARMCLK>,
<&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
<&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
<&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
<&cru HCLK_PDCORE_NIU>;
assigned-clock-rates =
<32768>, <1188000000>,
<100000000>, <491520000>,
<1400000000>, <600000000>,
<500000000>, <200000000>,
<100000000>, <300000000>,
<200000000>, <150000000>,
<200000000>;
};
Change-Id: I96dcaf9d40fdea58a4c3a823d91720203e0a75ad
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
|
||
|---|---|---|
| .. | ||
| regmap | ||
| clk-cpu.c | ||
| clk-dclk-divider.c | ||
| clk-ddr.c | ||
| clk-half-divider.c | ||
| clk-inverter.c | ||
| clk-mmc-phase.c | ||
| clk-muxgrf.c | ||
| clk-pll.c | ||
| clk-pvtm.c | ||
| clk-px30.c | ||
| clk-rk1808.c | ||
| clk-rk3036.c | ||
| clk-rk3128.c | ||
| clk-rk3188.c | ||
| clk-rk3228.c | ||
| clk-rk3288.c | ||
| clk-rk3308.c | ||
| clk-rk3328.c | ||
| clk-rk3368.c | ||
| clk-rk3399.c | ||
| clk-rk3568.c | ||
| clk-rv1108.c | ||
| clk-rv1126.c | ||
| clk.c | ||
| clk.h | ||
| Kconfig | ||
| Makefile | ||
| softrst.c | ||