Sandy Huang 50613be3c7 drm/rockchip: vop: set frame start to field start for interlace mode ... In interlace mode(480i60hz) the frame rate is 30hz, this is too low and lead to CTS test failed, so we use field start interrupt instead of frame start, and the vsync will update to 60hz. Change-Id: If73fb2b04dbd6749cc7cf899234a9f1e2283519e Signed-off-by: Sandy Huang <hjc@rock-chips.com>		2018-05-15 17:10:17 +08:00
..
arm	MALI: rockchip: Ensure that set voltage when update devfreq for the first time	2018-05-09 09:25:07 +08:00
drm	drm/rockchip: vop: set frame start to field start for interlace mode	2018-05-15 17:10:17 +08:00
host1x	rk: revert to v3.10	2015-11-11 15:57:28 +08:00
ipu-v3	drm/imx: Match imx-ipuv3-crtc components using device node in platform data	2016-06-07 18:14:37 -07:00
rogue	rk: add SPDX license identifier to files with no license	2018-01-31 20:56:06 +08:00
rogue_m	rk: add SPDX license identifier to files with no license	2018-01-31 20:56:06 +08:00
vga	vgaarb: fix signal handling in vga_get()	2015-12-11 14:04:44 +10:00
Makefile	MALI: add midgard src dir	2016-03-09 16:51:03 +08:00