Alvin Lee d170e938f0 drm/amd/display: On clock init, maintain DISPCLK freq ... [Description] - On init if a display is connected, we need to maintain the DISPCLK frequency - Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced) - Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged - However, add option to do a full pipe power down (including link) which will also avoid audio related issues - Disabled for the time being on dcn32 Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-04-11 18:03:35 -04:00
..
amdgpu_dm	drm/amd/display: Whitespace cleanup	2023-03-31 11:18:55 -04:00
dc	drm/amd/display: On clock init, maintain DISPCLK freq	2023-04-11 18:03:35 -04:00
dmub	drm/amd/display: [FW Promotion] Release 0.0.160.0	2023-03-31 11:18:54 -04:00
include	drm/amd/display: Add CRC and DMUB test support	2023-03-22 00:59:52 -04:00
modules	drm/amd/display: remove unused average_render_time_in_us and i variables	2023-04-11 18:03:22 -04:00
Kconfig	drm/amd/display: Rename DCN config to FP	2023-03-07 14:22:40 -05:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP	2023-03-07 14:22:39 -05:00
TODO