Nicholas Susanto cc4d6ea0f2 drm/amd/display: Fix DML2 logic to set clk state to min ... [Why] When an eDP with high clock states is going into s0i3, stream_count is 0. This causes DML to not update the clks to the lowest state and blocking us to enter s0i3 since eDP is out of vmin. [How] When stream_count is 0, set all the clocks to the lowest state. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2024-06-05 11:06:12 -04:00
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amdgpu_dm	drm/amd/display: Convert some legacy DRM debug macros into appropriate categories	2024-06-05 10:58:01 -04:00
dc	drm/amd/display: Fix DML2 logic to set clk state to min	2024-06-05 11:06:12 -04:00
dmub	drm/amd/display: Add params of set_abm_event for VB Scaling	2024-06-05 11:05:24 -04:00
include	drm/amd/display: fix graphics_object_id size	2024-05-29 14:48:31 -04:00
modules	drm/amd/display: Add array index check for hdcp ddc access	2024-05-02 16:18:17 -04:00
Kconfig	drm/amd/display: Fix invalid Copyright notice	2024-05-02 16:18:16 -04:00
Makefile	drm/amd/display: Refactor HUBP into component folder.	2024-05-08 15:17:03 -04:00