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cbce66669c
Support the USB PHY found on Google Tensor G5 (Laguna). This particular USB PHY supports both high-speed and super-speed operations, and is integrated with the SNPS DWC3 controller that's also on the SoC. This initial patch specifically adds functionality for high-speed. Co-developed-by: Joy Chakraborty <joychakr@google.com> Signed-off-by: Joy Chakraborty <joychakr@google.com> Co-developed-by: Naveen Kumar <mnkumar@google.com> Signed-off-by: Naveen Kumar <mnkumar@google.com> Signed-off-by: Roy Luo <royluo@google.com> Link: https://patch.msgid.link/20251227-phyb4-v10-2-e8caf6b93fe7@google.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
51 lines
1.4 KiB
Makefile
51 lines
1.4 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the phy drivers.
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#
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obj-$(CONFIG_PHY_COMMON_PROPS) += phy-common-props.o
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obj-$(CONFIG_PHY_COMMON_PROPS_TEST) += phy-common-props-test.o
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obj-$(CONFIG_GENERIC_PHY) += phy-core.o
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obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
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obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
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obj-$(CONFIG_PHY_GOOGLE_USB) += phy-google-usb.o
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obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
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obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
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obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
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obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
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obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o
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obj-y += allwinner/ \
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amlogic/ \
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apple/ \
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broadcom/ \
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cadence/ \
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freescale/ \
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hisilicon/ \
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ingenic/ \
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intel/ \
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lantiq/ \
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marvell/ \
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mediatek/ \
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microchip/ \
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motorola/ \
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mscc/ \
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nuvoton/ \
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qualcomm/ \
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ralink/ \
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realtek/ \
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renesas/ \
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rockchip/ \
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samsung/ \
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socionext/ \
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sophgo/ \
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spacemit/ \
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st/ \
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starfive/ \
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sunplus/ \
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tegra/ \
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ti/ \
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xilinx/
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