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Because phy1 is sata mode by default, and phy2 is pcie mode by default, when using qsgmii on phy1, it needs to be configured as pcie mode, because pcie mode is compatible with K28.1 and K28.5, while sata only has K28.5. If phy1 is in sata mode, qsgmii will not work, and both K codes need to be used at the same time. Based on this, we unified configuration into pcie mode. Signed-off-by: David Wu <david.wu@rock-chips.com> Change-Id: I4a9e5a2cdcee448ec3457778bf4ee7135be70087 |
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| allwinner | ||
| amlogic | ||
| broadcom | ||
| hisilicon | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| motorola | ||
| qualcomm | ||
| ralink | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| st | ||
| tegra | ||
| ti | ||
| Kconfig | ||
| Makefile | ||
| phy-core.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||