Dave Stevenson f5e8733d93 drm/vc4: hdmi: Allow DBLCLK modes even if horz timing is odd. ... [ Upstream commit 1d11896596 ] The 2711 pixel valve can't produce odd horizontal timings, and checks were added to vc4_hdmi_encoder_atomic_check and vc4_hdmi_encoder_mode_valid to filter out/block selection of such modes. Modes with DRM_MODE_FLAG_DBLCLK double all the horizontal timing values before programming them into the PV. The PV values, therefore, can not be odd, and so the modes can be supported. Amend the filtering appropriately. Fixes: 57fb32e632 ("drm/vc4: hdmi: Block odd horizontal timings") Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20220127135116.298278-1-maxime@cerno.tech Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-02-16 12:56:24 +01:00
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drm	drm/vc4: hdmi: Allow DBLCLK modes even if horz timing is odd.	2022-02-16 12:56:24 +01:00
host1x	gpu: host1x: select CONFIG_DMA_SHARED_BUFFER	2022-01-27 11:03:39 +01:00
ipu-v3	Updates to the interrupt core and driver subsystems:	2021-08-30 14:38:37 -07:00
trace
vga	vgaarb: don't pass a cookie to vga_client_register	2021-07-21 10:29:10 +02:00
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