George Shen c005a44f3a drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family ... [Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-07-25 13:36:32 -04:00
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amdgpu_dm	drm/amd/display: Add link encoding to timing BW calculation parameters	2023-07-18 11:15:51 -04:00
dc	drm/amd/display: Guard DCN31 PHYD32CLK logic against chip family	2023-07-25 13:36:32 -04:00
dmub	drm/amd/display: Correct grammar mistakes	2023-07-25 13:36:26 -04:00
include	drm/amd/display: Update 128b/132b downspread factor to 0.3%	2023-07-18 11:15:05 -04:00
modules	Revert "drm/amd: Disable PSR-SU on Parade 0803 TCON"	2023-06-30 13:11:36 -04:00
Kconfig	drm/amd/display: Allow building DC with clang on RISC-V	2023-07-21 16:52:25 -04:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP	2023-03-07 14:22:39 -05:00
TODO