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d4b00d132d
The am65_cpsw_iet_verify_wait() function attempts verification 20 times,
toggling the AM65_CPSW_PN_IET_MAC_LINKFAIL bit in each iteration. When
the LINKFAIL bit transitions from 1 to 0, the MAC merge layer initiates
the verification process and waits for the timeout configured in
MAC_VERIFY_CNT before automatically retransmitting. The MAC_VERIFY_CNT
register is configured according to the user-defined verify/response
timeout in am65_cpsw_iet_set_verify_timeout_count(). As per IEEE 802.3
Clause 99, the hardware performs this automatic retry up to 3 times.
Current implementation toggles LINKFAIL after the user-configured
verify/response timeout in each iteration, forcing the hardware to
restart verification instead of respecting the MAC_VERIFY_CNT timeout.
This bypasses the hardware's automatic retry mechanism.
Fix this by moving the LINKFAIL bit toggle outside the retry loop and
reducing the retry count from 20 to 3. The software now only monitors
the status register while the hardware autonomously handles the 3
verification attempts at proper MAC_VERIFY_CNT intervals.
Fixes:
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|---|---|---|
| .. | ||
| icssg | ||
| icssm | ||
| am65-cpsw-ethtool.c | ||
| am65-cpsw-nuss.c | ||
| am65-cpsw-nuss.h | ||
| am65-cpsw-qos.c | ||
| am65-cpsw-qos.h | ||
| am65-cpsw-switchdev.c | ||
| am65-cpsw-switchdev.h | ||
| am65-cpts.c | ||
| am65-cpts.h | ||
| cpsw_ale.c | ||
| cpsw_ale.h | ||
| cpsw_ethtool.c | ||
| cpsw_new.c | ||
| cpsw_priv.c | ||
| cpsw_priv.h | ||
| cpsw_sl.c | ||
| cpsw_sl.h | ||
| cpsw_switchdev.c | ||
| cpsw_switchdev.h | ||
| cpsw-common.c | ||
| cpsw-phy-sel.c | ||
| cpsw.c | ||
| cpsw.h | ||
| cpts.c | ||
| cpts.h | ||
| davinci_cpdma.c | ||
| davinci_cpdma.h | ||
| davinci_emac.c | ||
| davinci_mdio.c | ||
| k3-cppi-desc-pool.c | ||
| k3-cppi-desc-pool.h | ||
| Kconfig | ||
| Makefile | ||
| netcp_core.c | ||
| netcp_ethss.c | ||
| netcp_sgmii.c | ||
| netcp_xgbepcsr.c | ||
| netcp.h | ||
| tlan.c | ||
| tlan.h | ||