William Wu 4a9087f17c phy: rockchip: naneng-combphy: refactor the combphy_reg and ops ... This patch refactor the combphy_reg so that we can init PCIe/USB3.0/SATA/QSGMII separately. Change-Id: I8febce777a5b29948acdb66a1640245983cfe6cd Signed-off-by: William Wu <william.wu@rock-chips.com>		2020-11-09 09:58:09 +08:00
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allwinner	phy: sun4i-usb: fix dereference of pointer phy0 before it is null checked	2020-07-22 09:32:05 +02:00
amlogic
broadcom
hisilicon
lantiq
marvell
mediatek
motorola	phy: mapphone-mdm6600: Fix write timeouts with shorter GPIO toggle interval	2020-03-11 14:15:10 +01:00
qualcomm	phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init	2020-09-17 13:45:30 +02:00
ralink
renesas
rockchip	phy: rockchip: naneng-combphy: refactor the combphy_reg and ops	2020-11-09 09:58:09 +08:00
samsung	phy: samsung: s5pv210-usb2: Add delay after reset	2020-10-01 13:14:44 +02:00
st
tegra
ti
Kconfig
Makefile
phy-core.c	Revert "phy: add cp_test callback"	2020-06-29 16:53:21 +08:00
phy-lpc18xx-usb-otg.c
phy-pistachio-usb.c
phy-xgene.c