1.Support phy pll clk enable/disable is separated from
phy signal output.
2.Add avmute set/clear in resolution switching process.
3.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
4.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5f48b3292b434b26ab28a4e7238a87c8d64d5a33
e836764568