Ville Syrjälä ad193bc620 drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI ... The PCH transcoder registers are only 12 bits wide for the hdisplay and hblank_start values. On HSW/BDW the CPU side registers are 13 bits wide. intel_mode_valid() only checks against the higher limit (since we don't know where the mode is to be used), so an extra check is required against the FDI limits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180615174406.12258-3-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>		2018-06-19 17:18:24 +03:00
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drm	drm/i915: Enforce max hdisplay/hblank_start limits on HSW/BDW FDI	2018-06-19 17:18:24 +03:00
host1x	gpu: host1x: Use IOMMU groups	2017-12-21 14:52:36 +01:00
ipu-v3	gpu: ipu-v3: prg: avoid possible array underflow	2018-03-15 17:52:08 +01:00
vga	vga_switcheroo: Let HDA autosuspend on mux change	2018-03-13 22:58:49 +01:00
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