Shen, George aba3c3fede drm/amd/display: Clear DPCD lane settings after repeater training ... [Why] VS and PE requested by repeater should not persist for the sink. [How] Clear DPCD lane settings after repeater link training finishes. Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: George Shen <George.Shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-12-01 16:05:26 -05:00
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drm	drm/amd/display: Clear DPCD lane settings after repeater training	2021-12-01 16:05:26 -05:00
host1x	gpu: host1x: Plug potential memory leak	2021-09-16 18:06:52 +02:00
ipu-v3	media: i.MX6: Support 16-bit BT.1120 video input	2021-10-19 08:08:38 +01:00
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