Eric Yang a39a581669 drm/amd/display: fix inputting clk lvl into dml for RN ... [Why] Previous logic is only good for 15W parts. Other configuration need a smarter logic to match clk levels with pp table in the fuse. [How] Cache all 8 DPM level's clock data, find lvl that match each pstate in the pp table and build input into DML base on that Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-06 15:04:37 -05:00
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drm	drm/amd/display: fix inputting clk lvl into dml for RN	2020-02-06 15:04:37 -05:00
host1x	drm/tegra: Changes for v5.6-rc1	2020-01-15 16:21:28 +10:00
ipu-v3
vga	vga: Fix Kconfig indentation	2019-11-20 17:40:32 +01:00
Makefile