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TDA38640 can operate in either PMBus mode or SVID mode. In SVID mode, by design ENABLE pin is the only option for controlling the output rail i.e., ENABLE pin is chained to power good of another reglator & FPGA. In cases where the chip is configured for SVID mode, and the ENABLE pin is set at a fixed level or is left unconnected (with an internal pull-down), while requiring software control, the following workaround is necessary. The workaround utilizes ENABLE pin polarity flipping to control output rail. If property 'infineon,en-pin-fixed-level' is specified then determine if chip is in SVID mode by checking BIT15 of MTP memory offset 0x44 as described in the datasheet. If chip is in SVID mode then apply the workaround by 1. Determine EN pin level 2. Maps BIT7 of OPERATION(01h) to EN_PIN_POLARITY(BIT1) of PB_ON_OFF_CONFIG. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Link: https://lore.kernel.org/r/20230831190731.265099-3-Naresh.Solanki@9elements.com [groeck: Dropped unnecessary line continuation] Signed-off-by: Guenter Roeck <linux@roeck-us.net> |
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Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.