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Linux kernel source tree
8defec031c
and finally one new PLL rate for the rk3568 to fix display artifacts on a handheld devices based on that soc. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmVyLqUQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgcRmCACBK41MuaWd0yZdeQ0e/I1enSVESaWJSGtA A8abX1SkMADA7yclnLCqQYs+dExiuftL/okNzhWYWNW3GSZYSg2ayqzgewCFYcHq //+bLzikpxQM+UqobdRXkcrE7O0eDZEhQqhbSmvE/EDYtKWpovvS4jir5kBmbp+n zXOzQ2uYLcGcl20hme5LpqXURK+q0c6F76/PPgIzXXQDnaildZvL5Imb4LhSh8DL A4GWPJ8bAWfpFcFVWKW0ZF/HZlUX5X+3uyHTvZe1T1ctRiTePVTv6GNTptS3143A hBPMnSzficc6cUVSton+z6MCC9lJw8HtJCqw3luj7SNAyCWUktCg =oqhb -----END PGP SIGNATURE----- Merge tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Pull Rockchip clk driver fixes for the merge window from Heiko Stuebner: Fixes for a wrong clockname, a wrong clock-parent, a wrong clock-gate and finally one new PLL rate for the rk3568 to fix display artifacts on a handheld devices based on that soc. * tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name clk: rockchip: rk3128: Fix aclk_peri_src's parent clk: rockchip: rk3128: Fix HCLK_OTG gate register clk: rockchip: rk3568: Add PLL rate for 292.5MHz |
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Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.