linux/drivers/gpu
Uma Shankar 8b9bc7786a drm/i915/dram: Interpret 0xF populated-channel count as 16
Wa_16030862157:
Interpret 0xF populated-channel count as 16
The register MEM_SS_INFO_GLOBAL [Number of populated channels] field
definition is updated with an encoding for 16 channels.

For 16-channel configuration, program 1111b. A programmed value of 1111b
must be interpreted as 16 channels for memory bandwidth calculations.

The MEM_SS_INFO_GLOBAL populated-channel field is only 4 bits and cannot
encode 16, so on Xe3p the BIOS programs the saturated field value (0xf)
to indicate the fully-populated 16-channel config (4 memory controllers
x 4 channels). Interpret it as 16 and let the bandwidth math handle the
larger channel count.

v2: Limit the WA only till NVL (Suraj)
    Logical separation of WA (Vinod)

WA: 16030862157, 16030875223
Bspec: 69131, 79482

Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Link: https://patch.msgid.link/20260715143243.4141208-2-uma.shankar@intel.com
2026-07-21 13:44:39 +05:30
..
drm drm/i915/dram: Interpret 0xF populated-channel count as 16 2026-07-21 13:44:39 +05:30
host1x gpu: host1x: Fix iommu_map_sgtable() return value check 2026-05-28 17:19:30 +02:00
ipu-v3
nova-core drm-next for 7.2-rc1 2026-06-17 10:21:00 +01:00
tests
trace
vga fbdev: Wrap fbcon updates from vga-switcheroo in helper 2026-06-09 16:00:11 +02:00
buddy.c
Kconfig
Makefile