Victor Lu 8b22f04833 drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih ... Port this change to vega20_ih.c: commit afbf7955ff ("drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts") Original commit message: "Why: Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit if RB_ENABLE is not set. How to fix: Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set. The RB_ENABLE bit is required to be set, together with WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit would clear the RB_OVERFLOW." Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2024-10-22 17:50:40 -04:00
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drm	drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih	2024-10-22 17:50:40 -04:00
host1x	gpu: host1x: Use iommu_paging_domain_alloc()	2024-08-28 17:28:48 +02:00
ipu-v3	Driver core changes for 6.11-rc1	2024-07-25 10:42:22 -07:00
trace
vga	drm: Do delayed switcheroo in drm_lastclose()	2024-08-13 16:21:07 +02:00
Makefile