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8749061be1
SCIFA IP on RZ/G2L SoC has the same signal for both interrupt and DMA transfer request. Setting DMARS register for DMA transfer makes the signal to work as a DMA transfer request signal and subsequent interrupt requests to the interrupt controller are masked. Similarly clearing DMARS register makes signal to work as interrupt signal and subsequent interrupt requests to the interrupt controller are unmasked. Add SCIFA DMA tx support for RZ/G2L alike SoCs by disabling TXI line interrupt and setting DMARS registers by DMA api for DMA transfer request. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230412145053.114847-2-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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| .. | ||
| hvc | ||
| ipwireless | ||
| serdev | ||
| serial | ||
| vt | ||
| amiserial.c | ||
| ehv_bytechan.c | ||
| goldfish.c | ||
| Kconfig | ||
| Makefile | ||
| mips_ejtag_fdc.c | ||
| moxa.c | ||
| mxser.c | ||
| n_gsm.c | ||
| n_hdlc.c | ||
| n_null.c | ||
| n_tty.c | ||
| nozomi.c | ||
| pty.c | ||
| rpmsg_tty.c | ||
| synclink_gt.c | ||
| sysrq.c | ||
| tty_audit.c | ||
| tty_baudrate.c | ||
| tty_buffer.c | ||
| tty_io.c | ||
| tty_ioctl.c | ||
| tty_jobctrl.c | ||
| tty_ldisc.c | ||
| tty_ldsem.c | ||
| tty_mutex.c | ||
| tty_port.c | ||
| tty.h | ||
| ttynull.c | ||
| vcc.c | ||