Jon Lin c79cf2c1a8 phy: rockchip: naneng-combphy: Set gate_tx_pck_sel length select work for L1SS ... This configuration is required for Gen1 l1ss support. Change-Id: I921d1551dbbb4e85f823ce9ce0abbb96198d2ccf Signed-off-by: Jon Lin <jon.lin@rock-chips.com>		2022-05-21 16:43:56 +08:00
..
allwinner
amlogic
broadcom	phy: usb: Fix misuse of IS_ENABLED	2021-06-16 12:01:43 +02:00
cadence	phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()	2021-06-16 12:01:45 +02:00
freescale
hisilicon
intel	phy: intel: Fix for warnings due to EMMC clock 175Mhz change in FIP	2021-07-20 16:05:46 +02:00
lantiq
marvell	phy: marvell: ARMADA375_USBCLUSTER_PHY should not default to y, unconditionally	2021-05-14 09:50:13 +02:00
mediatek	phy: phy-mtk-tphy: Fix some resource leaks in mtk_phy_init()	2021-06-23 14:42:48 +02:00
motorola
mscc
qualcomm
ralink
renesas
rockchip	phy: rockchip: naneng-combphy: Set gate_tx_pck_sel length select work for L1SS	2022-05-21 16:43:56 +08:00
samsung
socionext	phy: uniphier-pcie: Fix updating phy parameters	2021-07-14 16:56:47 +02:00
st
tegra
ti	phy: ti: dm816x: Fix the error handling path in 'dm816x_usb_phy_probe()	2021-07-14 16:56:47 +02:00
xilinx
Kconfig
Makefile
phy-core-mipi-dphy.c
phy-core.c
phy-lgm-usb.c
phy-lpc18xx-usb-otg.c
phy-pistachio-usb.c
phy-xgene.c