linux/drivers/gpu/drm/amd/include
Lee Jones 8509479df3 drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as __maybe_unused
Fixes the following W=1 kernel build warning(s):

 In file included from drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c:28:
 drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:186:29: warning: ‘USB0_BASE’ defined but not used [-Wunused-const-variable=]
 186 | static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
 | ^~~~~~~~~
 drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:179:29: warning: ‘UMC_BASE’ defined but not used [-Wunused-const-variable=]
 179 | static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } },
 | ^~~~~~~~
 drivers/gpu/drm/amd/amdgpu/../include/sienna_cichlid_ip_offset.h:158:29: warning: ‘SDMA1_BASE’ defined but not used [-Wunused-const-variable=]
 158 | static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
 | ^~~~~~~~~~

NB: Snipped lots of these

Acked-by: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Cc: Likun Gao <Likun.Gao@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-24 12:09:53 -05:00
..
asic_reg drm/amdgpu: Add and use seperate reg headers for dcn302 2020-11-10 14:15:08 -05:00
ivsrcid drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) 2020-06-03 13:52:03 -04:00
amd_acpi.h
amd_pcie_helpers.h
amd_pcie.h
amd_shared.h drm/amdgpu: Add GFX Fine Grain Clock Gating flag 2020-11-04 17:08:08 -05:00
arct_ip_offset.h drm/amd/include/arct_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h drm/amd/pm: correct VR shared rail info 2020-10-27 11:58:57 -04:00
atomfirmware.h drm/amd/display: Add internal display info 2020-11-24 12:08:15 -05:00
atomfirmwareid.h
cgs_common.h drm/amdgpu: retire indirect mmio reg support from cgs 2020-04-09 10:43:18 -04:00
cik_structs.h
dimgrey_cavefish_ip_offset.h drm/amdgpu: initialize IP offset for dimgrey_cavefish 2020-10-12 14:00:20 -04:00
discovery.h drm/amdgpu/discovery: reserve discovery data at the top of VRAM 2019-10-15 15:48:46 -04:00
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h drm next for 5.10-rc1 2020-10-15 10:46:16 -07:00
kgd_pp_interface.h drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry (v2) 2020-11-13 17:29:45 -05:00
navi10_enum.h
navi10_ip_offset.h drm/amd/include/navi10_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi12_ip_offset.h drm/amd/include/navi12_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi14_ip_offset.h drm/amd/include/navi14_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
pptable.h
renoir_ip_offset.h drm/amd/display: Add DCN_BASE regs 2019-10-17 16:27:27 -04:00
sienna_cichlid_ip_offset.h drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
soc15_hw_ip.h
soc15_ih_clientid.h drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid 2020-06-03 13:52:04 -04:00
v9_structs.h
v10_structs.h
vangogh_ip_offset.h drm/amdgpu: add vangogh_reg_base_init function for van gogh 2020-10-05 15:14:02 -04:00
vega10_enum.h drm/amdgpu: Support new arcturus mtype 2019-09-13 17:35:48 -05:00
vega10_ip_offset.h drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused 2020-11-13 17:29:46 -05:00
vega20_ip_offset.h drm/amd/include/vega20_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
vi_structs.h