Akhil P Oommen 7e459c4126 drm/msm/a8xx: Fix ubwc config related to swizzling ... To disable l2/l3 swizzling in A8x, set the respective bits in both GRAS_NC_MODE_CNTL and RB_CCU_NC_MODE_CNTL registers. This is required for Glymur where it is recommended to keep l2/l3 swizzling disabled. Fixes: 288a932008 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Message-ID: <20260305-a8xx-ubwc-fix-v1-1-d99b6da4c5a9@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>		2026-03-05 13:49:50 -08:00
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drm	drm/msm/a8xx: Fix ubwc config related to swizzling	2026-03-05 13:49:50 -08:00
host1x	gpu: host1x: Syncpoint interrupt performance optimization	2025-11-14 18:27:19 +01:00
ipu-v3
nova-core	Driver core changes for 6.19-rc1	2025-12-05 21:29:02 -08:00
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vga
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