Algea Cao e836764568 drm/bridge: synopsys: dw-hdmi-qp: Optimize HDMI resolution switching process ... 1.Support phy pll clk enable/disable is separated from phy signal output. 2.Add avmute set/clear in resolution switching process. 3.To comply with the timing requirements of the HDMI protocol, HDMI must be enabled in tmds mode according to the following process: disable FRL -> enable/disable scramble —> power up phy 4.Optimize flt process Signed-off-by: Algea Cao <algea.cao@rock-chips.com> Change-Id: I5f48b3292b434b26ab28a4e7238a87c8d64d5a33		2022-08-16 10:53:51 +08:00
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analogix_dp.h	drm/rockchip: analogix_dp: Support DP connector	2022-03-24 19:03:30 +08:00
dw_hdmi.h	drm/bridge: synopsys: dw-hdmi-qp: Optimize HDMI resolution switching process	2022-08-16 10:53:51 +08:00
dw_mipi_dsi.h	drm/bridge: dw-mipi-dsi: remove the pclk which can be managed in runtime pm	2021-09-03 17:48:03 +08:00
mhl.h	drm/bridge/mhl.h: Replace zero-length array with flexible-array member	2020-03-06 11:52:01 +01:00