Chris Wilson 6f02958728 drm/i915: Use the correct GMCH_CTRL register for Sandybridge+ ... commit a885b3ccc7 upstream. The GMCH_CTRL register (or MGCC in the spec) is at a different address on Sandybridge, and the address to which we currently write to is undefined. These stray writes appear to upset (hard hang) my Ivybridge machine whilst it is in UEFI mode. Note that the register is still marked as locked RO on Sandybridge, so vgaarb is still dysfunctional. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2014-01-09 12:24:22 -08:00
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drm	drm/i915: Use the correct GMCH_CTRL register for Sandybridge+	2014-01-09 12:24:22 -08:00
host1x	drivers/gpu/host1x/drm: don't check resource with devm_ioremap_resource	2013-05-18 11:55:30 +02:00
vga	fbcon: fix locking harder	2013-02-08 12:02:43 +10:00
Makefile	gpu: host1x: Add host1x driver	2013-04-22 12:32:40 +02:00