Zheng Yang 6d29956712 drm/rockchip: hdmi: correct 3328 hdmi phy power up timing ... According to spec, TMDS driver should power up between PLL power up and PLL lock. There is an mistake of pdata en register, the real register is reg2 bit0, not reg1 bit0. Change-Id: I9d2b707cbcfd70b63f4a1a277a85f21b62643d2e Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>		2017-06-15 16:13:52 +08:00
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arm	MALI: fix thermal crash with booting up	2017-04-27 19:26:43 +08:00
drm	drm/rockchip: hdmi: correct 3328 hdmi phy power up timing	2017-06-15 16:13:52 +08:00
host1x	rk: revert to v3.10	2015-11-11 15:57:28 +08:00
ipu-v3	drm/imx: Match imx-ipuv3-crtc components using device node in platform data	2016-06-07 18:14:37 -07:00
rogue	RK3368 GPU version: Rogue L 0.22	2015-08-17 14:12:00 +08:00
rogue_m	GPU: Rogue_M: update to 1.31_2 version & support gpu pd.	2016-01-18 19:04:28 +08:00
vga	vgaarb: fix signal handling in vga_get()	2015-12-11 14:04:44 +10:00
Makefile	MALI: add midgard src dir	2016-03-09 16:51:03 +08:00