Christophe Leroy 6c5875843b powerpc: slightly improve cache helpers ... Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers that are summed to obtain the target address. Using 'Z' constraint and '%y0' argument gives GCC the opportunity to use both registers instead of only one with the second being forced to 0. Suggested-by: Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>		2019-07-05 01:35:10 +10:00
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asm	powerpc: slightly improve cache helpers	2019-07-05 01:35:10 +10:00
uapi/asm	KVM: PPC: Book3S HV: XIVE: Add a mapping for the source ESB pages	2019-04-30 19:35:16 +10:00